The dimensions of integrated circuit (IC) technology used for very large scale integration (VLSI) applications continues to be scaled-down. Circuit dimensions in the nanometer realm (sub-100 nm) and below increase the significance of interconnect delays and other signaling characteristics in such VLSI applications. For example, decreased conductor width causes increased interconnect resistance, and decreased conductor spacing causes an increase in interconnect capacitance. Three-dimensional effects, including fringing and interline coupling, increase as the ratio of conductor height to conductor width increases. Furthermore, scaled-down ICs may operate at higher frequencies.
Reduced IC dimensions can result in parasitic effects related to an interconnect becoming greater than the parasitic effects attributable to logic gates driving the interconnect, or greater than the parasitic effects attributable to logic gates driven by the interconnect. Gate delay may be improved while interconnect delays between gates are not improved, or are degraded.
As VLSI technology evolves, increased device densities provide greater capabilities in IC devices, and more devices and/or functionality may be provided on an IC device. Increased functionality may result in drastic increases in the number of transistors and interconnects, and may increase the average length of the interconnects in order to connect the circuit elements. Chip area is often limited by the area physically occupied by interconnects, and designers are motivated to scale-down the dimensions of the interconnects and increase the number of metal layers. These factors can lead to increased interconnect density.
Technology downscaling has produced decreased delays attributable to a transistor or logic gate (which may be referred to as “intrinsic delay”), which may be measured in the picosecond range for example. Technology down-scaling has not decreased delays attributable to interconnects (which may be referred to as “extrinsic delay”) at the same rate as transistor or logic gate with process evolution, due in part to reduced wire geometries that lead to increased resistance, capacitance of the interconnect and/or larger parasitic delays. As a result, interconnect delay has become a larger fraction of overall delay.
Uncertainty-aware interconnect Design for Manufacturability (DFM) guidelines are provided by foundries that manufacture VLSI devices using nanotechnology. Uncertainty-aware interconnect DFM plays an important role in the success of businesses. DFM can affect circuit performance as well impacting yield, cost and time-to-market. However, the limited DFM guidelines provided by foundries are often difficult for designers to apply in order to optimize the circuit layout with performance and area trade-off.
Accordingly, there exists a need for improvements in IC design processes.